The increase in complexity of signal processing algorithms demands an ever growing need for performance and power, where in most cases strict real time constraints need to be met.
Classical WCET approaches to solve these requirements, lead to inefficient architectures in terms of power dissipation, silicon area and high target clock frequencies.
Our approach is to take advantage of in deep knowledge of the signal processing algorithms and find efficient equivalent architectures featuring a fraction of the complexity of the straight forward implementations targeting ASIC or FPGA SoCs.
Besides pure hardwired architectures as well advanced heterogeneous multiprocessor architectures will be taken into account for the decision of the design space.
By using our in house developed design flow which incorporates a SystemC modeling approach using our profiling and exploration environment NoCTrace, we have the freedom to choose from a wide range of possible solutions to find the optimal architecture in an early design stage.
- A H.264 Video Coprocessor for Mobile DVB-H Terminals
- MPEG-4 Video Codec SOC for Mobile Multi Media Applications