Signal processing applications dedicated for programmable processor architectures (DSPs) getting more and more complex, which results in an increasing demand for computational performance. In the past this performance increase has been achieved by raising the clock frequency. Due to the physical limitations of nowadays silicon technologies, parallel processing systems are the way to solve this problem of increasing performance demand. Parallel processing systems for embedded signal processing differ significantly in their architecture in respect to the used processor architecture and their communication infrastructures compared to general purpose systems. Whereas in the general purpose computing domain homogeneous multi/many processor architectures with an SMP approach dominate in the embedded signal processing field heterogeneous multi/many core architectures with specialized interconnection topologies can be found.
If it comes to multi/many core architectures the interconnection topology and the design of the memory subsystem and hierarchy is even equally important as the architecture of the used processor cores itself, whereas the well known “memory wall” effect limits the effective use of a big number of processor cores working simultaneously.
Our research in this field focusses on the design of application specific processors, accompanied specialized instruction sets and interconnection dedicated to multi media signal processing.
- ESG IPconnect streaming interface for signal processing IPCores
- ESG NoC Network on Chip
- ESG NoC Monitoring System
- SIMD Engine Processor for H.264 processing