Hardware Solutions

HEVC Real-time Hardware Decoder

The H.265 / MPEG-HEVC ultra low delay decoder IP core is completely hardware based, and supports the HEVC main profile. Even without an additional processor core the decoding providing real-time performance for full HD resolution (1080p30) at a clock frequency below 150 MHz. The design is currently implemented on an Altera Stratix-V FPGA.

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Real-time Stereo-to-Multiview Conversion - IP core and FPGA reference implementation for depth estimation

Real-time stereo-to-multiview conversion allows playback of 3D Blu-ray content or any other stereoscopic 3D video content on autostereoscopic displays. Costly offline conversion is no longer needed and personal 3D viewing preferences can be adjusted on-the-fly. Depth estimation, the heart of stereo-to-multiview conversion, is now available as a pure hardwired IP core suited for FPGA and ASIC implementation. For evaluation purposes a reference FPGA implementation can be provided.

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Enhanced Low Latency Video Codec, Ultra Low Latency Video Codec

Fraunhofer HHI offers a range of H.264 /AVC compliant codecs (IPs) for use in industrial applications. Specially tailored to real-time applications, the IPs allow coding of up to 1080p resolution on current FPGA technologies. The codecs are fully hardwired implementations with low power consumption and minimal resource usage.