HEVC 4K Real-time Hardware Decoder

Real-time hardware decoding on FPGAs

Fraunhofer HHI has developed a completely hardware based H.265 / MPEG-HEVC decoder IP core. Without an additional processor core, the decoder achieves real-time performance for 4K ultra high definition (UHD) video requiring only moderate clock frequencies. For evaluation purposes the design is available as an implementation for the Altera Stratix V GX Advanced Systems Development Kit (4K /UHD) and the Altera Stratix V DSP Kit (up to 1080p60).

Specifications

  • HEVC Main and Main 10 Profile conformance
  • Optional HEVC Range Extensions conformance for Main 4:2:2 (10) Profile
  • 1080p60 10-bit real-time decoding even on mid-range FPGAs
  • 4K/UHD 10-bit real-time decoding on powerful FPGAs (at least Stratix V)
  • Fully hardwired implementation, no need for an additional processor core
  • Standard interfaces for easy SoC integration
  • Low logic utilization approx. 70k ALM*
  • IP core available as FPGA netlist or VHDL code for ASIC implementation
  • Comprehensive synthesis and test bench environment

*Altera Stratix V ALMs